Flash memory, which is a form of non-volatile memory, has become an increasingly popular means of electronic data storage. Flash memory is particularly advantageous to traditional magnetic forms of memory storage, as it is more durable and allows for faster data accesses. In a standard flash memory, data is stored across a plurality of floating-gate transistors, known as “cells”, typically in large blocks. Each cell functions like a standard metal-oxide-semiconductor field-effect transistor (MOSFET) with the exception of a second (“floating”) gate, electrically isolated between the standard control gate and the MOSFET channel, acting in a capacitive capacity for storing electric charge thereon. Accordingly, each cell is capable of storing a single bit, or multiple bits, of data based on the charge of the floating gate. For example, an uncharged floating gate may correspond to logic “1” bit of data, while a sufficiently (negative) charged floating gate may correspond to logic “0” bit of data. Cells are typically initialized (and reset) to a logic “1” state (i.e. no negative charge is initially stored on the floating gate), and may be subsequently programmed (i.e. written) to a logic “0” state. To the contrary, individual cells (within a block) may not be independently reset from a logic “0” state back to a logic “1” state, due to flash memory architecture constraints. In other words, large blocks of cells are generally erased all at once.
Flash memory is typically found in two different varieties: NOR and NAND. The main difference between NOR and NAND flash memories lies in the configuration of the cells. Cells of a NOR memory are coupled to a bit line in parallel, thus allowing individual access to each of the cells. On the other hand, cells of a NAND memory are coupled to a bit line in series, thus operations are typically performed across the entire series of cells coupled to the bit line at a time. However, the series configuration of cells allows for the cells to be placed in closer proximity to one another, resulting in more densely packed memory arrays. This makes NAND memory advantageous by utilizing smaller die area for greater data storage capacity. However, up until now the way in which data is programmed, within a NAND flash memory, has severely limited the speed and efficacy at which program operations may be performed, thus limiting the use of NAND memory primarily to mass-storage devices. At the same time, the increasing use of NAND flash memory in portable electronic applications such as laptop computers and digital cameras has necessitated faster program speeds (e.g. video recording).
FIG. 1A illustrates a prior-art NAND memory device 100, made up of a bit line BL coupled to a plurality of cells 1200-120n (for purposes of discussion, it is assumed that each of the cells 1200-120n is a floating-gate transistor modeled after an NMOS). A bit line select transistor 110 is coupled between the bit line BL and the first cell 1200, and a ground select transistor 130 is coupled between the last cell 120n and a source terminal (e.g. a ground potential). Data is programmed into the memory device 100, one cell at a time, by applying a high program voltage VPGM to the word line for the desired cell, and applying a pass voltage VPASS to the word lines of all of the remaining cells. For example, programming a bit of data into the cell 1201 requires first lowering the bit line BL to a low voltage (˜0V). The word line WL1 is then raised to a suitable program voltage VPGM (˜20V) while the remaining word lines WL0 and WL2-WLn are brought to a pass voltage VPASS (˜10V). Next, a high voltage VCC is applied to the bit select line BS which effectively “turns on” the bit select transistor 110, while a low voltage (˜0V) is applied to the ground select line GS which effectively “turns off” the ground select transistor 130. Accordingly, the pass voltage applied to the word lines WL0 and WL2-WLn are sufficiently above a threshold voltage VT to allow the respective cells 1200 and 1202-120n to conduct, regardless of any stored charge on their floating gates, thus allowing the high program voltage applied to the gate of cell 1201 to induce electron tunneling onto the floating gate of the cell 1201. An unfortunate constraint of this approach is that only one of the cells 1200-120n coupled to the bit line BL may be programmed at a time. In other words, each row (e.g., group of one or more cells each coupled to the same word line WL, often referred to as a “page”) of cells 1200-120n is typically programmed sequentially. It should be noted that, for purposes of discussion, only a single bit line is shown with respect to the memory device 100 of FIG. 1A. However, the NAND memory device 100 may have two or more bit lines BL displaced substantially parallel to one another, such that the bit lines 13L and the word lines WL0-WLn are each coupled to an array of memory cells.
Still referring to FIG. 1A, data may be read from the NAND flash memory device 100, one cell at a time, by applying a low read voltage VRD to the word line for the desired cell and applying the pass voltage VPASS to all of the remaining cells. Continuing from the previous example, in order to read out the data stored in the cell 1201, the bit line BL is first charged to a voltage VBL. The word line WL1 is then brought to a read voltage VRD while the remaining word lines WL0 and WL2-WLn are once again brought to the pass voltage VPASS(˜10V). Now when the bit line select transistor 110 and the ground select transistor 130 are turned on, the negatively stored charge on the floating gate of cell 1201 effectively raises the threshold voltage VT of cell 1201 above the read voltage VRD, thus maintaining the cell 1201 in a non-conducting state. Accordingly, the charge on the bit line BL remains at the voltage VBL, and may be sensed and interpreted as a logical “0” bit of data. Alternatively, the presence of charge on the bit line BL may be sensed and interpreted as a logical “1” bit of data. On the other hand, if no charge was stored on the floating gate of cell 1201 (representing a logical 1 bit of data), then the application of the read voltage VRD may sufficiently induce cell 1201 into a conducting state thus forming a path to ground. In such case, the charge on the bit line BL is pulled low, and may be sensed and interpreted as a logical “1” bit of data. Alternatively, the absence of charge on the bit line BL may be sensed and interpreted as a logical “0” bit of data.
FIG. 1B illustrates another prior-art NAND memory device 160 made up of multiple NAND memory chains 101 and 102. Memory chain 101 is made up of a bit select transistor 110, a first plurality of cells 1200-120m, and a ground select transistor. Memory chain 102 is made up of a bit select transistor 140, a second plurality of cells 120m+1-120n, and a ground select transistor 150. The operation of NAND memory device 160 is very similar to that of the NAND memory device 100, as described above in reference to FIG. 1A, with the exception that the two memory chains 101 and 102 may be operated on separately. For example, turning on bit select transistor 110, while leaving bit select transistor 140 off, allows for programming to occur only within the cells 1200-120m. This allows more cells to be coupled to the bit line BL while, at the same time, reducing power consumption. It is important to note that, individually, each of the memory chains 101 and 102 operates exactly the same as the memory device 100, of FIG. 1A.
It is also important to note that programming is generally completed on a first one of the cells 1200-120n before programming may begin on a second one of the cells 1200-120n, to ensure accurate programming of data. Thus, a programming operation still requires turning on exactly one of the bit select transistors 110 or 140, and applying a program voltage VPGM to exactly one of the world lines WL0-WLn. For example, a programming of cell 1200 would require first lowering the voltage of the bit line BL (˜0V). Next, bit select transistor 110 is turned on by raising the voltage on the bit select line BS_A to a voltage VCC, at the same time bit select transistor 140 is held off by applying a low voltage (˜0V) to the bit select line BS_B. A program voltage VPGM is then applied to the word line WL0, while a pass voltage is applied to all of the remaining word lines WL1-WLn. During this programming operation, both ground select transistors 130 and 150 are held in the “off” state. Similarly, read operations may be performed in the manner discussed above in reference to FIG. 1A.
FIG. 1C illustrates a timing diagram for a program operation within a NAND flash memory. The program operation of FIG. 1C is herein discussed in reference to the memory device 160 of FIG. 1B. At time t0 the bit line BL is brought low. At this time the first bit select line BS_A is set to a voltage VCC and the word line WL0 is set to a voltage VPGM, while the word lines WL1-WLm are set to a voltage VPASS and the second bit select line BS_B and the remaining word lines WLm+1-WLn remain deasserted (for purposes of discussion, when referring to the signal levels on the word lines WL0-WLn, application of a program voltage VPGM is represented as an “asserted” signal, application of a pass voltage VPASS is represented as an “asserted but non-programming” signal, and application of a zero voltage is represented as a “deasserted” signal). The word line WL0 remains asserted for the duration of time t0 to t1 needed to program data into cell 1200, and the first bit select line BS_A also remains asserted for this entire duration, as discussed above in reference to FIGS. 1A and 1B. At time t1, after the program operation in cell 1200 has completed, the first bit select line BS_A and the word lines WL0-WLm are deasserted, allowing the bit line BL to return to a non-programming state.
Then at time t2, the bit line is once again brought low. At this time the second bit select line BS_B is set to the voltage VCC, the word line WLn is set to the voltage VPGM, and the word lines WLm+1-WLn−1 are set to the voltage VPASS. During this time the first bit select line BS_A and all other word lines WL0-WLm remain deasserted. The word line WLn remains asserted for the duration of time t2 to t3 needed to program data into cell 1200, and the first bit select line BS_A also remains asserted for this entire duration. It should also be noted that, although not shown in the illustration of FIG. 1C, the ground select lines GS_A and GS_B are constantly held low during the program operations.
The sequence of program operations in the example above may take a long time to complete, as a second program operation generally begins only after a first program operation is fully completed (i.e. only one of the word lines WL0-WLn may be asserted at any given time).
FIG. 2 illustrates another prior-art NAND memory device 200 made up of an array of cells 2210-221n and 2220-222n, two bit lines BL1 and BL2 each coupled to a respective column of cells, via bit select transistors 211 and 212 and ground select transistors 231 and 232, and a plurality of word lines WL0-WLn each coupled to a respective row of cells. Note that, in FIG. 2, a voltage applied to any particular one of the word lines WL0-WLn is received at the gates of two cells. For example, a program voltage VPGM applied to the word line WL1 places both cells 2211 and 2221 in a program state. In order to prevent an accidental programming of cell 2221 when programming cell 2211, the bit line BL2 should first be charged to a high voltage VCC. When the bit select transistor 212 is turned on, while the ground select transistor remains off, the current from the bit line BL2 creates a channel (˜7V) across each of the cells 2220-222n. The voltage difference is small enough to prevent electrons from tunneling into the floating gates of any of the cells 2220-222n, regardless of the voltages (VPASS or VPGM) applied to the respective word lines WL0-WLn. However, this places a further constraint on the programming of a NAND flash memory device 200, as the cells, coupled to separate word lines WL0-WLn, of separate bit lines BL1 and BL2 are also programmed one at a time. In other words, only one of the word lines WL0-WLn may be set to a program voltage VPGM, at any given time, across the entire array of cells 2210-221n, and 2220-222n. Accordingly, there exists a need for NAND flash memory devices with faster program speeds.